The present invention relates to digital circuits, particularly circuits for generating a plurality of phase shifted clocks from a phase locked loop circuit (PLL). In particular, the present invention relates to methods and apparatuses for generating phase shifted clocks at various local sites on an integrated circuit (IC) chip from a minimal set of signals from a central PLL.
Recent advances in miniaturization and fabrication techniques permit circuit designers to create a PLL circuit directly on board the chip on which logic circuitry, say a microprocessor, is implemented. The availability of an onboard PLL circuit facilitates logic designs which advantageously utilize one or more phase shifted clocks. Phase shifted clocks are clocks that have essentially the same frequency relative to one another and are delayed, or phase shifted, from one another in a frequency-dependent manner. Phase shifted clocks advantageously simplify the design and improve the performance of certain types of logic circuits, such as dynamic CMOS logic circuits or positive feedback amplifiers, in which the relative timing between clocks as well as circuit cycles are important at any operating frequency. For further information regarding phase-shifted clocks in general, reference may be made to the commonly-assigned, co-pending patent application Ser. No. 08/448,886 entitled "Rubberband Logic" (Attorney Docket No. P710/SUN1P017) and filed on May 24, 1995, which application is incorporated herein by reference for all purposes.
In the prior art, multiple phase shifted clocks are generated at a centrally located PLL and are then bussed across the chip via separate conductors to the local sites where they are used. It has been subsequently discovered, however, that the use of multiple conductors to bring the centrally generated phase shifted clocks to the local sites where they are needed has many disadvantages.
FIG. 1 shows in a simplified format a prior art PLL circuit for centrally generating a plurality of phase shifted clocks, including the conductors necessary to bus the centrally generated phase shifted clocks across chip. Referring now to FIG. 1, there is shown an integrated circuit (IC) chip 100, having a centrally located PLL 102. As the term is used herein, a PLL is considered to be centrally located if the circuit that performs the function associated with the PLL is centralized at a single location on chip, regardless whether that location is at the chip center or near the chip's periphery. Centrally located PLL 102 generates a plurality of phase shifted clocks and buses some or all phase shifted clocks to each of the three local sites, i.e. local sites 104, 106, and 108. For simplicity of illustration, FIG. 1 shows PLL 102 generating six phase shifted clocks which are outputted on six conductors 111-116. All six conductors 111-116 are furnished to local site 106 where they are required. Five of the conductors, 112-116, are brought to local site 104 for local usage. Another five, 111-115, are further brought to local site 108 for use at that location. As is apparent, a large number of conductors are required in the prior art to furnish centrally generated phase shifted clocks to the local sites where they are needed.
When phase shifted clocks are generated centrally, a large number of conductors are required to bus the centrally generated phase shifted clocks to the local sites. The use of a large number of conductors disadvantageously consumes space, i.e. real estate, on chip, often necessitating an increase in chip size to accommodate the aforementioned large number of conductors within existing design rules. The large number of conductors on chip also complicates the layout task and places a limitation on the total number of clocks that can be centrally generated. Because of these limitations, the use of multiple phase shifted clocks in circuit designs has not gained wide acceptance since it is often impractical, due to real estate, layout, and power constraints, to centrally generate more than a few phase shifted clocks and to bus them across chip.
In the prior art method which generates phase shifted clocks centrally and bus them across chip, the presence of long conductors, each carrying a high frequency clock, increases the susceptibility of the resulting design to electromagnetic interferences. Further, the capacitances associated with these long conductors necessitate a higher driving current on the part of the central PLL, thereby increasing power consumption and resulting in the undesirable production of thermal energy that is frequently the cause of premature chips failures.
More significantly, when phase shifted clocks are centrally generated, the addition or deletion of a clock at a local site necessitates changes throughout the chip. For example, when one clock out of say five is no longer needed at a local site in the prior art, the conductor that buses that clock signal from the central PLL to the local site needs to be removed and the layout may need to be reoptimized. If a designer decides in a later stage of a design project to substitute one clock line for another clock line, conductors have to be rerouted in the prior art to furnish the appropriate clock lines to the local site that requires them. Design modularity is therefore adversely impacted, with an attendant increase in design time and costs whenever changes have to be made with respect to one of the centrally generated clocks.
What is needed is improved apparatuses and methods for generating phase shifted clocks at local sites from as few centrally generated PLL signals as possible. The improved apparatuses and methods would simplify the design of the central PLL by preferably generating only a reference clock and a reference signal, from which phase shifted clocks can be locally generated on an as-needed basis. In this manner, the number of conductors radiating from the central PLL may be reduced, thereby lowering the chip's real estate usage, power consumption, and susceptibility to electromagnetic interference.